IWLPC (Wafer-Level Packaging) Conference Proceedings


FABRICATION OF TAPERED THROUGH-VIAS ON (100) SILICON FOR WAFER-LEVEL PACKAGING

Authors: Huang Shuang Wu and Chia Yong Poo
Company: Micron Semiconductor Asia Pte Ltd.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Increasing demand for high-performance, high-density, lowpower, smaller-sized portable electronic gadgets is driving the development of subsystem integration onto a single integrated circuit (IC) component. Methods of integration can be system-on-a-chip (SoC), system-in-a-package (SiP), and wafer-level packaging (WLP); currently, SiP is the most preferred method because only tested-good subsystems are integrated, thus producing a higher yield. Die- or waferlevel integration of these subsystems using through-silicon vias is one of the best methods to form a small-footprint, high-performance SiP.

This paper presents a silicon etching method to create through-wafer interconnections for die- or wafer-level threedimensional (3D) integration and stackable IC packages. Focusing on the development of chemical wet-etch methods to fabricate tapered through-vias on (100) silicon wafers, the team evaluated IC surface protection during wet-etch processing. The affecting factors of through-via integrity, such as surface smoothness, contamination, and mask design and misalignment were also investigated. In addition, the team studied the effect of process temperature and etchant concentration on etch rates and characterized the profile and quality of through-vias. The as-formed throughvias are coated with dielectrics and metals, such as Ti/W, as well as Cu layers so as to provide an electrical path for further IC stacking.

Keywords: through-via, IC protection, anisotropic etch, wafer-level packaging



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