IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Christian Val, Ph.D. and Pascal Couderc, Ph.D.
Company: 3D PLUS
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: We know that what drives the packaging of dice for consumer products are:
  • Volume/weight decrease (X, Y – AXIS), size, Thin (Z)
  • Cost: reduced packaging cost and System level costs
  • Ease of integration for Systems in Package (logic/memory, logic/analog, logic/RF, analog/MEMS).

  • Considering the State of the Art, several technological approaches have been made.

    It can first be noted that what is named Package-on- Package (PoP) consists in fact in stacking 2 nonstandard 3-D modules which we named Proprietary Package. We therefore have a Proprietary Package-on- Proprietary Package rather than a Standard Package-on Standard Package. This constitutes the difference between a one-source product and a multi-source product.

    The PoP interconnection is carried out with balls, which, on the one hand increases the package surface and on the other hand poses the general problem of a second reflow of the balls when the customer carries out the surface mounting of this module.

    Also, the fact that it is not moulded will allow the external elements (Flux, dust, humidity) to later create corrosions and leakage currents.

    3D PLUS approach, which we named Standard Package-on-Standard Package (SPoSP) allows to avoid these inconveniences. The customer can for instance use standard memories, packaged in available and lowcost TSOP packages; Their stacking with bare dice such as microcontrollers, ASIC, etc is carried out as per our 3-D standard technique.

    These Chip-on-Chip techniques have the big advantage of using the Back-End equipments, which are available worldwide. However, they have the important disadvantage to use area because of the wires. Also, we are faced with all the problems linked to the multi chip modules i.e. manufacturing global yields. As a matter of fact, if no KGD are used (generally not available and very expensive), the yield begins to lower beyond 3 or 4-stacked dice.

    We use our 3-D standard technique, which we adapted to the Wafer Level Process technologies.

    We named this technology “Wireless Die-on-Die (“WDoD”) to show that it is wireless and that consequently the area of the “WDoD” 3-D module is almost identical to the area of the larger dice.

    In order to avoid the well-known yield problems, we use the concept of the Known Good rebuilt wafer, i.e. we rebuild a wafer only with the good-tested dice.

    The stacking of these rebuilt wafers with our mature 3-D technique does not present any particular problem.

    As a summary, the criteria which have been retained when we launched this important European programme in 2001 are the following:
  • Use of multisource standard wafers
  • Use of non-Thinned wafers
  • Use of RLC passive components, for example Philips PICS technology
  • Stacking of 8 to 10 levels per mm
  • Electrical test of each level prior to stacking thanks to the test on the “rebuilt wafer”
  • This process is totally collective from A to Z steps.

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