IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Peter C. Salmon
Company: Peter C. Salmon, LLC
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: A new concept for fabricating very low profile fullybuffered dual in line memory modules (VLP FB-DIMMs) is proposed. Interconnection layers are built up on copper panels using high resolution photolithography. The copper substrate provides a built-in heat spreader. 8-high die stacks are employed. A new Copper-Pillar-Well (CPW) flip chip connector is used; it provides convenient rework of all 144 memory chips in each module, without melting any solder. The same connectors enable the Advanced Memory Buffer (AMB) chip to be attached within the width limitation of 18.3 mm for the VLP module. Improved electrical, thermal and mechanical properties are potentially achievable, enabling 16 GByte modules having advanced specifications.

Keywords: FB-DIMM, CPW, copper substrate, 80Au20Sn, stacked package, rework, memory module, HDI, 3D semiconductor.

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