IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Kimberly D. Pollard, Ph.D., Raymond Chan, Ph.D., a
Company: Dynaloy, LLC
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: FlipChip (FC) and Wafer Level Packaging (WLP) are two of the fastest growing segments in the integrated circuit (IC) packaging industry. The practice of incorporating FC or bump technology in devices is experiencing significant growth, due to the improvement it provides in power and ground distribution, with the attendant reduction in simultaneous switching noise, (SSN). The demand for WLPs is increasing due to their small form factor and the increased demand for portable products.

Both FC and WLP technologies impose significant new demands related to the materials used for permanent dielectric layers and photoresists for fabrication processes. Cleaning chemistry must be designed to remove highly cross-linked films such as photoresists and fluxes; but keep the solder bump, exposed metals, under-bump metallization (UBM), and dielectrics undamaged. Device reliability and performance rely heavily on the proper working of all these components. In situ or discrete analytical procedures are required for testing the reliability of the materials used.

Typical quality assurance and control procedures for fabrication monitor the appearance (surface condition, shape) of the solder bumps. Wafer or device inspections are commonly performed by optical microscopy, and indicate if the device is free of photoresist after cleaning, and whether or not metal remains after etching.

The focus of this paper is defect formation during lead-free wafer level packaging. The defect type that the talk will concentrate on is referred to as the ‘white ring’ defect. It is found at the base of electroplated bumps and first becomes visible to the line operator in the bumping process after the thick photoresist is removed.

Key words: wafer bumping, defects, photoresist removal

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