IWLPC (Wafer-Level Packaging) Conference Proceedings


PLACING WAFER LEVEL DEVICES IN A HIGH SPEED WORKFLOW

Author: Gheorghe Pascariu
Company: Hover-Davis Inc.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The electronics industry has long anticipated the arrival of advanced chip packaging that leverages the design advantages of bare die. With suppliers and manufacturers now facing the greater challenge of placing more die at higher speeds, the need to meet this demand has been overwhelming.

The concept of eliminating intermediate packaging costs while feeding flip chip devices at high speeds from wafer format, plus combining the SMT and Semiconductor placement process is the future for meeting tomorrow’s demands.



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