PLACING WAFER LEVEL DEVICES IN A HIGH SPEED WORKFLOWAuthor: Gheorghe Pascariu
Company: Hover-Davis Inc.
Date Published: 11/1/2006 Conference: IWLPC (Wafer-Level Packaging)
The concept of eliminating intermediate packaging costs while feeding flip chip devices at high speeds from wafer format, plus combining the SMT and Semiconductor placement process is the future for meeting tomorrow’s demands.
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