IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Todd P. Oman
Company: Delphi Corporation
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Power semiconductors require electrical interconnects to both sides of the die and a highly conductive thermal path. These requirements are typically satisfied by employing wire-bonds whether using direct chip attach to the substrate or a package solution. The wire-bond process is an expensive, serial process which precludes heat sinking from the top-side of the die. Additionally, power semiconductors typically have active circuitry under the metallization of the bond locations making them vulnerable to mechanical damage during the bonding process. A method to achieve the top-side interconnects without the shortcomings of the wire-bond process has been developed that also facilitates vertically stacking of the die. This method of interconnection is compatible with high power devices due to its low thermal resistance. The interconnect hardware, SPDC (Stacked Power Die Contact), is also compatible with existing surface mount process flows and equipment, thus simplifying implementation. The SPDC incorporates traces and vias through a dielectric material that provides the required isolation between the gate and source of a die and the drain of the adjacent die. Reliability testing has demonstrated that this method exceeds the automotive goal of a minimum life of 1000 thermal cycles for temperature extremes of -40 to +150ºC.

Key words: power, silicon, stacked, vertical integration.

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819