WAFER-TO-WAFER AND CHIP-TO-WAFER INTEGRATION SCHEMES FOR SYSTEMS-IN-A-PACKAGE AND 3D INTERCONNECTSAuthors: Thorsten Matthias, Stefan Pargfrieder, Herwig Kirc
Company: EV Group Inc.
Date Published: 11/1/2006 Conference: IWLPC (Wafer-Level Packaging)
Layer transfer on wafer level using aligned wafer bonding has the advantages of higher throughput, enhanced cleanliness, and the flexibility that standard fab equipment can be used. 3D stacking using chip-to-wafer bonding focuses on the yield, the “good known die” issue. Dies of different size can be integrated, e.g. several small dies on one big base die, enabling unchallenged small form factors. Furthermore the dies can be produced on different substrate materials, on different wafer sizes, and in different fabs by different producers. This flexibility results in very short time-to-market. The modular concept allows integrating standard components, which significantly reduces the development costs.
Very often the thinned dies have to be processed on both sides prior to bonding. A new ultra-thin wafer handling concept based on temporary bonding enables to process the back-thinned wafers using standard equipment. Precise alignment of the temporarily bonded wafers and subsequent permanent wafer bonding are key for achieving high performance devices. In this paper the recent advances in the integration and handling schemes are discussed with a higher emphasis on the manufacturing requirements.
Key Words: System-in-a-package, 3D interconnect, wafer bonding, 3D integration schemes
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