IWLPC (Wafer-Level Packaging) Conference Proceedings


WAFER-LEVEL PACKAGING: EFFECTIVE COST REDUCTION WITH WAFER BONDING

Authors: Thorsten Matthias, Markus Wimplinger and Paul Lind
Company: EV Group Inc.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The market demands for ongoing price reductions in consumer electronics require novel and innovative manufacturing processes. Packaging of the devices is a major cost factor, and therefore continual reduction of the packaging costs is key.

Wafer bonding enables first-level packaging on the wafer level, which has been introduced 15 years ago for automotive devices. Due to the very short product life cycles in consumer electronics, sometimes only a few months, the choice of the appropriate bonding method is driven by the potential for continual cost reduction. Depending on the product, innovative bonding processes using SU-8 and BCB, but also the established MEMS processes like metal-metal and direct bonding, can be the right choice. The decision criteria are:

Highest yield on all manufacturing process is imperative. This involves not only the bonding process, most important pressure and temperature uniformity, but also the pre-processing steps like cleaning and plasma activation. Integration of the pre-processes in the wafer bonding platform enables real-time process control. Due to the accurate timing of the process flow the bonding process time can be optimized and the capacity and throughput are increased.

Very high wafer-to-wafer alignment accuracy allows minimized substrate real estate consumption of the gasket enabling both, more chips per wafer and a higher production capacity. The SmartView® alignment principle reduces the manufacturing steps, as no backside alignment keys are needed, and reduces the material costs as backside polished wafers are not necessary.

Process compatibility between R&D and production equipment significantly reduces cost and time for process qualification. A modular and redundant equipment concept results in high uptime with no trade-offs.

In this paper the technical differences for established and modern wafer bonding processes are reviewed. The impacting factors on cost reduction for current and upcoming product generations are analyzed in detail.

Key Words: wafer-level packaging, wafer bonding, wafer alignment, yield enhancement



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