DRIE WITH HIGH RATE AND UNIFORMITY FOR MEMS AND WLPAuthor: Leslie Lea
Company: Surface Technology Systems plc
Date Published: 11/1/2006 Conference: IWLPC (Wafer-Level Packaging)
Limitations of current packaging are driving the investigation of advanced packaging schemes. System-in Package (SiP) focuses on fabricating 3D stacks of chips in a single package. Systems might include processing capability, memory and sensors. Via holes must be etched through wafers and then metallized, in order to form inter-layer contacts. Via holes can be precisely fabricated using the Advanced Silicon Etch process (ASER), a version of the Bosch time multiplexed etch process.
Packaging of optical devices such as CCD image sensors is becoming particularly important. For Chip Scale Packaging (CSP), plasma etching may be used effectively to etch scribe channels, and additionally through wafer vias.
As the manufacture of devices moves from 150mm wafers to 200mm wafers it becomes increasingly important to design plasma processing equipment that is capable of achieving very high etch uniformity over the larger wafer size and high etch rate to reduce the cost of ownership. STS has followed a program of extensive continuous development of plasma process tools and silicon etch processes for the last decade.
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