IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Eric Laine, Klaus Ruhmer, Luc Belanger, Michel Tur
Company: SUSS MicroTec, Inc. and IBM
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: High-end microelectronic packaging is increasingly moving from wire bonds to solder bumps as the method of interconnection. Flip chip in Package (FCiP) requires many small bumps on tight pitch whereas Wafer Level Chip Scale Packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing and the direct attach of preformed solder spheres. Each of these technologies has important limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for this entire range of solder bump pitch.

C4NP is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/soft contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications.

This paper provides a summary of the most recent manufacturing and reliability results of C4NP bumped, 300mm wafer, high-end logic device packaging. This includes reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is also included. Relevant process equipment technology and the novel requirements to run a HVM (high volume manufacturing) C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBM’s packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec.

Key Words: Flip chip, wafer bumping, lead free, CSP

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