IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Arthur Keigler, Bill Wu, Jim Zhang and Zhenqiu Liu
Company: NEXX Systems, Inc.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Electrodeposited copper pillar structures provide advantages for some packaging applications. Economical manufacturing requires maximizing the deposition rate while achieving the coplanarity, flatness, and morphology required by the overall packaging process. Copper pillars are typically 50 to 80 microns tall with diameters from 40 to 100 microns. Adjacent heat sink pad structures may be formed during the same plating operation. Deposition control is strongly mediated by the organic additive package and depends sensitively on boundary layer thickness. This paper describes the effects of deposition rate on the process operating window for various pattern structures.

Key words: flip chip, wafer bumping, electroplating, copper, WLCSP

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