HYBRID WAFER-LEVEL PACKAGING FOR RF-MEMS APPLICATIONS
Authors: J. Iannacci, M. Bartek, J. Tian, S. Sosin, A. Akhn Company: ARCES-DEIS Università di Bologna and HiTeC-DIMES, Date Published: 11/1/2006
IWLPC (Wafer-Level Packaging)
Abstract: In this work, we present our progress in development of a wafer-level packaging (WLP) solution suitable for RF-MEMS devices and enabling hybrid co-integration of additional IC dies. The proposed approach is based on a capping high-resistivity silicon substrate that is wafer-level bonded to an RF-MEMS device wafer. The capping substrate contains electroplated through-substrate copper vias for signal redistribution to an area-array solder bumps and recesses for accommodation of RF-MEMS devices. Optionally, through-substrate cavities or recesses are realized for hybrid integration of additional IC dies. Several aspects of this packaging solution are studied. First of all, the packaging process flow details are briefly described. Then the options of achieving a hermetic/semi-hermetic sealing of the packaged cavities are investigated together with description of the corresponding process flows. Furthermore, co-integration of RF-MEMS devices and CMOS control circuitry based on hybrid-packaging approach is discussed. For this purpose, two solutions where the capping substrate facilitates the placement of CMOS dies are introduced. Finally, package electromagnetic characteristics are analyzed and the technological degrees of freedom (e.g. via diameter, capping substrate thickness, etc.) are used to optimize the package radio-frequency (RF) behavior. The experimental results of the first fabricated sample of capped test structures (50O transmission lines and shorts) are presented and compared to the simulations.