OVERVIEW OF MEMS WAFER LEVEL PROCESSES AND PATENTS
Authors: Ken Gilleo, Ph.D. Company: ET-Trends LLC Date Published: 11/1/2006
IWLPC (Wafer-Level Packaging)
Abstract: MEMS, the technology that adds mechanical elements to electronic chips is one of the most important fields of the 21st century. The MEMS industry continues to grow at a steady pace that will begin to accelerate as more advanced devices move from lab to fab. But many unique challenges remain for both fabrication and packaging. Micro-Electro-Mechanical Systems (MEMS) manufacturing methods tap into the semiconductor industry so that the “MEMS factories” already exists. Electronic circuitry can be fabricated on the same wafer as the mechanical elements to build “smart” MEMS chips. But MEMS wafers, unlike “pure” electronic chips, are typically fragile and extremely sensitive to micro-contamination as might be expected. One solution to mechanical shock and micro-particle contamination sensitivity is to exploit waferlevel processing. Today, MEMS wafers are capped and hermetically sealed at wafer-level, but most commercial processes are far from optimization. Commercial methods typically use multi-step capping processes followed by double-singulation to separately release the cap and MEMS chip. But the resulting capped MEMS chip is only a “prepackage” that must still go through a “final packaging” step. The capped chip can often be overmolded once the mechanical elements are protected from direct contact with molding compound. But some capped MEMS devices must be packaged in cavity enclosures to avoid the stress of encapsulant shrinkage. New wafer-level processes, especially those that produce a complete package, have been proposed and may achieve commercial success. This paper will provide an overview of existing methods and new processes, including a survey of the most recent patents and pending applications.