IWLPC (Wafer-Level Packaging) Conference Proceedings


SiP – IDENTIFYING ISSUES FOR STACKED (3D) MULTICHIP PACKAGING ADOPTION

Author: Larry Gilg
Company: Die Products Consortium
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The term “packaging” as applied to microelectronics, delineates the materials, processes and methods for providing a satisfactory electrical, mechanical and thermal operating environment for an integrated circuit (IC). The resulting “packaged” device is termed a module. The term multi-chip module (MCM) was introduced in the mid-1990s as a technology that incorporated several unpackaged ICs on an interconnecting substrate. There was a flurry of activity to develop high-performance interconnecting substrates that could wring the utmost in performance from the bare, bumped or TAB’ed IC device. Advanced packaging came to be viewed as a value added process that offered the utmost performance with the smallest form factor (size and weight) for critical applications where cost was not the prime consideration. The resulting MCM developments gained a reputation as overpriced solutions good for solving niche problems only.

However, as makers of portable and handheld systems analyzed the opportunities for building smaller, lighter and higher performing devices with greater functionality, the benefits of the multi chip packaging approach using die products became clear. The challenge then became to develop designs and assembly technologies that result in a lower cost than traditional surface mount devices, allowing faster time to market than the system on chip solutions. The enabling factor in these advanced packaging technologies is reliance on die products.



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