SiP – IDENTIFYING ISSUES FOR STACKED (3D) MULTICHIP PACKAGING ADOPTIONAuthor: Larry Gilg
Company: Die Products Consortium
Date Published: 11/1/2006 Conference: IWLPC (Wafer-Level Packaging)
However, as makers of portable and handheld systems analyzed the opportunities for building smaller, lighter and higher performing devices with greater functionality, the benefits of the multi chip packaging approach using die products became clear. The challenge then became to develop designs and assembly technologies that result in a lower cost than traditional surface mount devices, allowing faster time to market than the system on chip solutions. The enabling factor in these advanced packaging technologies is reliance on die products.
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