IWLPC (Wafer-Level Packaging) Conference Proceedings


ASSEMBLING OPTICAL DEVICES UTILIZING WAFER LEVEL TECHNOLOGY AND CHIP ON BOARD PROCESS TO ENABLE HIGHER YIELDS AND REDUCED COSTS

Authors: Yehudit Dagan, Giles Humpston, and Michael J. Nyst
Company: Tessera Inc.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Device manufacturers using a chip on board (COB) process to attach image sensors or other optoelectronic devices to a circuit board have long sought means by which to increase yields and therefore reduce overall costs. While COB has certain advantages over traditional packaging, such as short signal path and small low profile, the process results in lower yields than competing technologies due to contamination of the optical sensor during the assembly process. Preventing contamination becomes an even greater issue for higher resolution (mega-pixel) image sensors, where the effect of contamination from dust particles is compounded by the small size of the pixels. Furthermore, as future camera modules become more complex, requiring additional assembly, tuning and calibration, unprotected image sensors will be exposed to dust particles over a longer time span.

The author will present the concept of integrating waferlevel packaging of optical devices with COB assembly processes. The resulting technology, SHELLCASE® CF, permits attaining high assembly yields regardless of the imager resolution, which in turn reduces the cost of the final product.



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