IWLPC (Wafer-Level Packaging) Conference Proceedings


SURFACE CLEANING FLIP CHIP WAFERS FOR TEST AND ASSEMBLY IMPROVEMENTS

Author: Terence Collier
Company: CVInc.
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Flip chip wafers are dirty compared to the wafers that are processed in the front end fab. The wafer and bumps have layers of carbon contamination, residues and non-desirable oxides that are unfounded in the front end. These contaminants not only can impact assembly yield but reduce the overall test yield as well. Proper cleaning helps recover yield loss, reduce cycle time and rework.

Keywords: Flip chip, cleaning, test, yield enhancement, CRES



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