IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: W. Christiaens, B. Vandevelde, E. Bosman, and J. V
Company: IMEC/TFCG Microsystems
Date Published: 11/1/2006   Conference: IWLPC (Wafer-Level Packaging)

Abstract: This contribution describes modelling and technology for an Ultra-Thin Chip Package (UTCP), based on the embedding of ultrathin dies in flexible substrates. Chips with thickness in the range of 20 - 30 µm are packaged in between 2 polyimide layers. The result is a very thin chip package, with a total thickness of only 50 - 60 µm. Chip, PI layers and metal are so thin that the whole package is bendable.

The base substrate is a uniform polyimide layer, applied (spin coated and cured) on a rigid carrier. Then the ultrathin chip is placed and fixed, using BCB as die attach material. Next, the second spin-on polyimide layer is applied and cured. Vias to the contacts of the chip are laser drilled and the contact metal layer is sputtered and photolithographically patterned. This metal layer is providing a fan out to the contacts of the chips. Finally the whole package is released from the rigid substrate.

The resulting package can be SMD assembled on PCB or flex, or can be embedded in a stack of PCB layers, replacing for example the naked die - with the advantage that alignment constraints for the embedded package are not as severe as for the embedded die. Also the “Known Good Die” (KGD) issue is solved as the packaged chip can be tested before embedding. UTCP’s have also the potential for stacking in order to obtain 3D type chip packages.

Key words: chip packaging, 3D, flexible

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