PACKAGE ON PACKAGE (PoP) STACKING AND BOARD LEVEL RELIABILITY RESULTSAuthors: Lee Smith, Moody Dreiza, and Akito Yoshida
Company: Amkor Technology, Inc.
Date Published: 9/24/2006 Conference: SMTA International
PoP stacking is experiencing high rates of adoption in handheld multimedia electronic applications as a result of the total cost, technical and business logistic benefits PoP provides vs. alternative 3D packaging technologies. PoP represents the next level of 3D packaging, designed to integrate high density digital logic, plus high capacity and combination memory devices in a package stacked structure through SMT processing in the final product assembly flow. System and component designers, surface mount assembly and reliability engineers will benefit from this paper which addresses the range of design, component, assembly and reliability considerations necessary to successfully launch PoP stacking in high volume applications.
Daisy chain PoP test vehicles were used is these studies, designed with three separate nets (bottom BGA to mother board, stacked interface and stacked interface corner balls) to facilitate stacking yield measurement and enable continuous reliability monitoring to characterize failure modes in drop, bend and temperature cycling. One pass reflow package on package SMT stacking was utilized with standard flux and paste materials assembled on JEDEC test boards.
The multiple PoP studies and test legs to be reported will cover a variety of common package sizes, Pb free material sets and underfill options to summarize their stacking yields and reliability performances.
KEY WORDS and ACRONYMS 3D packaging, stacked package, package on package, PoP, package stackable very thin fine pitch BGA, PSvfBGA, system in a package, SiP, multi-chip package, MCP, stacked CSP, board level reliability, BLR, solder joint reliability, SJR
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