Pan Pacific Symposium Conference Proceedings


3D PACKAGING ENABLED WITH ELECTROCHEMICAL DEPOSITION TECHNIQUES FROM VARIED ELECTRONIC INDUSTRY SEGMENTS

Authors: Dan Schmauch, Bioh Kim, and Tom Ritzdorf
Company: Semitool, Inc.
Date Published: 1/17/2006   Conference: Pan Pacific Symposium


Abstract: As product requirements and consumer demands drive higher integrated circuit functionality into smaller packages, new techniques for manufacturing and packaging are required. Amongst these are various techniques being used and developed for 3D packaging or “chip stacking”. Any new approach comes with risk, and there are reasons to question whether much of this technology is indeed practical[1], so there is strong motivation to adopt and/or adapt existing technologies to this relatively new advanced packaging application. The list of these “leveraged” technologies is quite long. This work focuses specifically on evaluating the electrochemical deposition techniques that have been “borrowed” from other areas of the semiconductor and related electronic industry segments to help enable 3D packaging. We compare the economic and technical scales of the originating segment to the requirements of each deposition technique in 3D packaging applications. Examples of several cases have been evaluated, and practical cases are presented. Deep via for chip-to-chip (or wafer-to-wafer) interconnect: In order to fully realize the potential of vertically stacked ICs, many deep and through via technologies are under consideration. This area is perhaps the rifest with examples of leveraged technology. Copper deposition chemistries and structures have been borrowed both from the printed circuit board (PCB) segment, with much larger feature sizes, and from the IC interconnect segment, with drastically smaller features. Deep features require organic additives, advanced power supply waveforms, and other methods for reliable, repeatable fill.[2] Electrochemical methods developed for damascene interconnect can also be used for enhancement and repair of sputtered seed layers in high aspect ratio vias. Compression-based connections using lined rather than fully filled vias[3] also utilize electrochemical methods similar to those familiar to III-V compound semiconductor manufacturing. Alloy deposition: Although PbSn solders have long been deposited for wafer level packaging applications, the increasing requirement for alternate, lead-free solders introduces the need to deposit alloys which are more difficult to control than traditional lead-based solders. Techniques from the thin-film head industry, long familiar with challenges in alloy co-deposition, have been demonstrated to make possible more options to successfully deposit consistent lead-free solders. Other leveraged technologies include liners and barriers deposited with electroless – rather than electrolytic – methods, which have been modified further from PCB, Cu interconnect, and traditional electroless nickel, immersion gold packaging structures.



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