Pan Pacific Symposium Conference Proceedings


THREE DIMENSIONAL HETEROGENEOUS CHIP INTEGRATION PROCESS

Author: David R. Scheid
Company: Honeywell, Inc.
Date Published: 1/17/2006   Conference: Pan Pacific Symposium


Abstract: Demand has recently increased for high-density packaging solutions to meet the needs of the high performance computing, medical, communications, defense, portable and sensor market segments. Three-dimensional stacking schemes promise the technical advantages of better silicon packaging efficiency, resulting in less interconnect delay, reduced power and increased speed. A number of bare dice stacking technologies are emerging to provide low weight and compact portable systems. This paper presents a method for vertically integrating thin chips, using a seamless fine pitch build-up process to make contacts directly to the bare die. The vertical interconnects are made using proven thin film deposition techniques on a planar substrate with standard wafer level processing equipment in a clean room environment to achieve high yields. The process has been designed so that vias can be located anywhere to eliminate the IO bottleneck at the chip interface, and to possibly add extra functionality or testability to the completed module. The material choices for the multilevel interconnect structure and the excellent dimensional control achieved when working with a silicon substrate permits much finer dimensions for routing signals than the current capability of flex circuits or other substrates. These high density thin film routes can be designed within a controlled impedance environment and also utilize Copper metallization to realize very low packaging parasitics. The processing sequence avoids the handling issues associated with working with thin die, since the wafer thinning operation is completed last. In addition this process lends itself to the incorporation of passive capacitor and resistor networks. The process is very flexible so both logic and memory die can be combined to produce a three-dimensional (3D) system in package (SIP) solution. The resulting module can be placed within a traditional hermetic package or it can be used to form the basic building block for additional stacking solutions. This module has enhanced reliability since one of the assembly interfaces has been eliminated. The additional benefits of this packaging technology that will be presented are listed below: • Continues Moore’s law, while also increasing performance • Provides for better device yield and optimization • Reduces power while improving the I/O bandwidth • Shortens design cycles times and reduces mask cost with better first pass success • Eliminates the chip IO bottleneck and accommodates all die pad layouts and pitches • Enhanced reliability due to the reduction of assembly interfaces • Exploits the assembly industry infrastructure and can utilize JEDEC standards • Provides the basic building block for other die stacking and 2nd level interconnect solutions



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