Pan Pacific Symposium Conference Proceedings


C4NP: LEAD-FREE AND LOW COST SOLDER BUMPING TECHNOLOGY FOR FLIP CHIP AND WLCSP

Authors: Klaus Ruhmer, Daniel Fleming, Ph.D., and Peter Gru
Date Published: 1/17/2006   Conference: Pan Pacific Symposium


Abstract: Today, various solder bumping technologies are being used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres.1 However, all these established technologies have important limitations for fine pitch bumping with lead-free alloys: Evaporation is too costly in general, solder paste printing often does not provide the desired bump stand-off height when it comes to fine-pitch bumping, electroplating is found to be expensive and difficult to control for lead-free alloys and preformed solder spheres are only applicable for a pitch down to approximately 500 microns. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions until 2010 from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry. C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as WLCSP bumping applications. This paper reviews the current status of the first C4NP lines installed at semiconductor manufacturers. It discusses the relevant process equipment technology and a manufacturing cost model. Last but not least, the presentation includes manufacturing data provided by IBM’s packaging operation at the Hudson Valley Research Park in East Fishkill, NY.



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