IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Yogi Ranade, Prashant Singh and Anwar Ali
Company: LSI Logic
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Wafer level packaging is commonly used today as a packaging solution for applications requiring ultra-small package form factors. This paper discusses some of the technology drivers for its adoption, its unique benefits, silicon level design considerations and some challenges that need to be addressed as the technology proliferates through higher I/O counts and densities.

Applications of Wafer Level Packaging in SoC ASIC designs are considered. While traditional WLP are typically low I/O count and die size, WLP processes can be used to develop flexible and interchangeable wirebond and flip chip packaged solutions. Wafer level packaging methodology applied to ASIC design offers an opportunity for IP re-use with little incremental development effort. Effective codesign of ASIC silicon and RDL layers taking into account signal integrity, ESD, and electromigration issues can achieve this. Furthermore ASIC flip chip designs using low-K silicon Inner Layer Dielectric layers and FSG can make use of the lowK BCB materials to further reduce routing parastics in silicon layers.

Keywords: Wafer level packaging, ASIC design, signal integrity

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