IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Peter C. Salmon
Company: Sysflex, Inc.
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: A conceptual design is described for a stacked 3D electronic subsystem that achieves a miniaturization factor of over 100 compared with current assemblies, yet it can be well-tested, repairable, and adequately cooled. Cooling channels are provided between each module in the stack. All functionality in the subsystem is implemented on IC chips, including digital, analog, RF, integrated passives, optical, and test functions. The chips are attached to copper substrates using re-workable flip chip connectors, and the substrates are stacked using ball grid arrays. The subsystem is repairable down to the chip level; this is a fundamental advantage that can lead to complex systems having advanced performance and high reliability.

Reliability is potentially high because conventional cables and connectors are eliminated, the subsystem is mechanically rugged, cooling is improved, and a better integration of heterogeneous chips is provided. The integrated cooling channels support heat dissipations up to 1W/mm2 of chip surface, including optimal allocations of cooling resources to hot spots on a die. Since the flip chip connectors have an inductance ~ 0.1 nH and high-performance interconnections are provided on the copper substrates, signaling rates of at least 20 Gbps for digital signals and 10 GHz for RF signals should be achievable.

Keywords: 3D electronic subsystem, re-workable flip chip, cooling channels, repair-ability, heat bumps, electro-optic connector, stacked BGA, SiP, copper BGA.

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