IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Rajiv Roy and Tim Schafer
Company: August Technologies
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Manufacturers can lose millions of dollars to bump connectivity and adhesion defects. To help boost yields, or protect against potential losses, operations incorporate advanced macro inspection, 2D bump inspection, 3D bump inspection, and backside inspection to automatically collect data after each process step. The data includes an image of the wafer, and a wafer map that indicates whether each die passed or failed inspection. By capturing defects, or their causes, when they originally surface in-process, engineers have the data they require to identify underlying process or equipment issues and ultimately boost yields. This paper describes how advanced macro inspection technologies can be used to collect information from seven common processes that create round, solder bumps—versus flat-top column bumps—as shown in Figure 1.

Keywords: bump inspection, 2D bump inspection, 3D bump inspection, adhesion, connectivity, CD lines, redistribution, post-passivation layer.

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