IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Christian VAL
Company: 3D PLUS
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: After the important Wafer Level packaging study carried out with LETI, THALES, IBS, ST MICROELECTRONICS, CYBERNETICS etc, a very interested application has been launched. After the first 3-D stacking stages, which allowed to reach volumes of around 1 cm3, these studies led us to build 3-D modules of around 1 mm3 only. One application is currently being carried out for a Californian company. It is about a micro stimulator for muscles and nerves. The module comprises 5 ASIC in bare dice, and the total dimensions of the module are 0.7 X 1.4 X 4 mm, i.e. 3.9 mm3.

The manufacturing of this type of 3-D module is based on following criteria : use of standard dice (non thinned dice) .no KGD (too expensive) .test of each level prior to stacking. In order to perform this breakthrough, we use a technique named “Rebuilt Wafer”, the thinning being carried out after all the other operations of pad redistribution. The thinning of the rebuilt wafer leads to a thickness of 125 µm. Some outstanding studies will allow to find out how far down we could go.

After the test of each unit which composes this rebuilt wafer, it is diced as would be done with a silicon wafer, the stacking being carried out as per the technique which we have been using from the start at 3D PLUS. Two applications will be presented, one concerns highspeed SRAM memories, the other one this micro stimulator.

Key words : Wafer level packaging, stacking.

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