IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: N. Saito, R. Kiumi, and F. Kuriyama
Company: Precision Machinery Company, Ebara Corporation
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: As three-dimensional (3D) packaging offers the promise of high-performance integration with the highest density of IC functions, it is spreading out to 3D packaging applications. It is emerging as the solution for microelectronics development toward system-on-chip and system-in-package. The 3D flip chip structures with through silicon vias have very good potential for the implementation of 3D packaging. We have been developed the Cu electroplating technology of making via filling on 3D packaging for five years. In our study, we used a dip-type electroplating machine UFP-300 for the Cu via filling.

The electroplating chemicals were composed of copper sulfate, sulfuric acid, hydrochloric acid and several kinds of additives of leveler, suppressor and accelerator. We found that the direct current plating was suitable for via filling, and electric current density was about 5mA/cm2 for higher aspect ratio via filling, and the chemicals could be flowed over a wafer surface uniformly by using the dip type of plating machine. The increasing of uniformity on over plated Cu film thickness could decrease polishing burden on removing Cu over-plating.

In our study, optimization was realized by adjusting plating conditions, and the nonuniformity of plated Cu film thickness was controlled being smaller to about 5-6% on a whole wafer, which was evaluated by means of the resistance meter Kokusai Electric VR-120. As a result, we fabricated the Cu through electrodes of diameter 5-50 µm, depth 35-150 µm, and aspect ratio 1.5-10. In this paper, we also discussed the effective factors and the fabrication processes on formation of Cu via filling in 3D packaging.

Key Words: via filling, through electrodes, electroplating, 3D packaging

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