IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: R.J. Gutmann, J.J. McMahon, S. Rao, F. Niklaus and
Company: Rensselaer Polytechnic Institute Center for Integr
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Three-dimensional (3D) integration with through-die vias offer improved electrical performance compared to edgeconnected wire bonds in stacked-die assemblies for wireless applications. Monolithic wafer-level 3D integration offers the potential for a high density of micron-sized through-die vias necessary for highest performance memory stacks, microprocessors with large L2 caches and ASICs with large embedded memories. In addition, such wafer-level technologies offer the potential of lowest cost in large manufacturing volume of any heterogeneous integration platform, incorporating the inherent low cost of monolithic IC interconnectivity.

After a brief summary of current wafer-level 3D integration platforms, a recently introduced platform that offers the process integration advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength and environmental robustness of dielectric adhesive bonding using benzocyclobutene (BCB) is discussed. Critical processing challenges of the new platform include BCB partial curing compatible with damascene patterning, postdamascene-patterning cleaning and surface activation, bonding process parameters, and wafer-level planarization requirements. The inherent incorporation of a redistribution layer into the bonding layer process further reduces the process flow and is compatible with wafer-level packaging (WLP) technologies.

Key words: 3D, high-density interconnect, wafer-level, redistribution layers.

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