IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: M.Puech, B. Andrieu, L.Popin, N.Launay, N.Arnal, P
Company: Alcatel Vacuum Technology
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: This paper presents the latest developments in Deep Reactive Ion Etching (DRIE) for the integration of passive components (L,C) on Silicon or Glass wafers and recent results for Wafer-Level Packaging applications (WLP).

The DRIE technique, which has been accepted as a key enabling technology for the manufacturing of MEMS/MOEMS products is gaining more interest in the field of microelectronics. In the first part of this paper, we will present the latest DRIE results of “Pyrex” and Silicon applied to manufacturing of passive devices like high Q inductors and 3D silicon capacitors. In the second part, we will review the different DRIE steps related to 3D stacking of multiple chips at the wafer level.

We will also discuss the advantages of ICP etching of silicon for stress relief after wafer thinning process. Then, smooth tapered trenches at high etch rate for the wafer encapsulated technology and deep etching of via holes for WLP technologies will be presented. Finally, we will introduce DRIE as a powerful, low damage alternative to the conventional die separation techniques.

Key words: DRIE, passive components, Wafer-Level Packaging.

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