IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Thorsten Matthias et al.
Company: EV Group
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Wafer-level packaging via wafer bonding allows smaller and thinner packages, improves the yield due to higher cleanliness, enables the encapsulation of vacuum or process gas and finally reduces the packaging costs significantly. High precision alignment of device wafer to cap wafer allows real chip size packaging as the required width of the sealing rings is in the low micron range. Furthermore different functional subsystems like ASIC and MEMS can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. Vertical interconnects between the wafers allow 3D integration.

The wafer bonding technique has to be compatible with CMOS processing and with standard back end of line procedures. The bonding/annealing temperature is limited due to active devices on the wafers. Cu-Cu thermocompression bonding, plasma activated low temperature fusion bonding and adhesive layer bonding are the established methods.

Aligned wafer bonding enables two different techniques for 3D integration. The first approach is to align and bond the independently processed wafers prior to back thinning. This way the first wafer acts as carrier for the second wafer during back thinning, and no special thin wafer handling is required. The second approach is to bond one device wafer temporarily to a sapphire carrier using a thermal or UV release tape or dedicated wax. The bulk silicon is totally removed via grinding, etching and polishing and then the remaining layer is bonded permanently to the second device wafer applying Cu-Cu thermo compression bonding, adhesive layer bonding or fusion bonding. Finally the temporary bonding is released. Due to the low thickness of the layer, the wafer gets transparent and through wafer alignment methods can be applied allowing alignment accuracy of 0,5µm (3s). Both techniques can be repeated multiple times.

In this paper the two approaches are compared based on the key parameters alignment accuracy and bond quality. The capabilities and limitations of current equipment is analysed in detail.

Key Words: 3D Interconnect, wafer-level packaging, wafer bonding, wafer alignment, layer transfer, thin wafer handling, plasma activation, low temperature processing

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