IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Moody Dreiza, Lee Smith, Akito Yoshida, and Jonath
Company: Amkor Technology
Date Published: 11/3/2005   Conference: IWLPC (Wafer-Level Packaging)

Abstract: This paper outlines the methodology and guidelines for effective stacked package on package (PoP) designs. PoP stacks currently in production or development, consist of a bottom package containing a high density logic device designed to receive a mating top memory package typically containing high capacity or combination memory devices. An OEM achieves lowest cost and maximum logistical benefits, when these two components are sourced from different IC device suppliers then stacked in the final product PWB assembly flow.

Thus, a design methodology that facilitates close collaboration across the supply chain is recommended to optimize PoP designs. Further, this methodology must be structured to support development of industry design standards to enable reuse of technology, sourcing flexibility and stimulate broader package stacking infrastructure development. PoP stacks are complex mechanical and electrical structures, so design collaboration and standards are critical to help address the various system and device related design trade-offs to achieve the optimum balance of product cost, size, performance and time to market requirements.

Since PoP was developed to leverage the current design and assembly infrastructure in place for combination memory devices delivered as multi-chip packages (MCP) also called stacked die chip scale packages (S-CSP), this article will focus on the PoP design flow, with emphasis on the assembly and substrate guidelines for the bottom - package stackable very thin fine pitch BGA (PSvfBGA) developed within Amkor.

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