SMTA International Conference Proceedings


Authors: Bala Nandagopal et al.
Company: Cisco Systems, Inc.
Date Published: 9/25/2005   Conference: SMTA International

Abstract: As the electronics industry transitions into Pb-free technology, many companies which require very high product reliability may still continue to use SnPb interconnect technology until 2010. Memory components are one commodity space where the suppliers are ahead in driving the transition to Pb-free packaging technology.

Thus, many manufacturers are forced to use these Pb-free packages within SnPb assembly reflow process. This is typically termed a Backward Compatible assembly. The purpose of this paper was to study a Pb-free DDR2 CSP memory package using SnPb solder, at peak temperatures of 210oC, 220oC and 227oC. Control SnPb and Pbfree assemblies, having the same alloy for the solder ball and the solder paste, were also included for comparison.

Often it is easier to get any peak temperature needed by solely assembling the package that is of interest onto a test vehicle. A test vehicle was designed to mimic an actual product which would include very large flip chip BGAs, connectors, leaded packages, and temperature-sensitive electrolytic capacitors. This would introduce actual product-like temperature distributions and bring forth any issues to consider in reflow and rework profile development while achieving the targeted joint and body peak temperatures, as well as assembly body and peak temperatures of adjacent SnPb parts while reflowing/reworking at 227oC peak temperatures.

Microstructures of solder joints and intermetallic formation were characterized for the backward compatible and control tin-lead and lead-free assemblies. Also, the microstructural changes due to double sided reflow of backward compatible joints, which would essentially undergo two reflows, were studied. Package pull testing was performed to study the failure modes among SnPb, Pb-free and backward compatible assemblies. Solder mechanical strength was evaluated through shock testing for both single-sided and mirror imaged component assemblies. All of the process development, microstructure study, package pull test and shock test were performed on two OSP board thicknesses, 2.3mm with 10 copper layers and 3.1mm with 16 copper layers.

Keywords: DDR2, backward compatible, assembly

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