APPLICATION OF A NEAR INFRARED DEFECT INSPECTION PROCESS FOR FLIP CHIP ASSEMBLYAuthor: L. Todd Woods et al.
Company: Plexus Corp
Date Published: 9/25/2005 Conference: SMTA International
One example is the high accuracy measurement of the placement of bare die and Flip Chip devices. Typically, the mechanical dimensioning of diced silicon is roughly ± 25 microns making the use of the cut edge as a measurement reference impossible if the accuracy requirements are finer. Some optical devices such as Vertical Cavity Surface Emitting Lasers (VCSEL) have placement accuracy requirements of less than 2 microns to avoid active alignment.
The addition of fiducials on the back of the silicon has been attempted, but this is a secondary process and the correlation of the fiducial to the critical feature is often inadequate to meet the alignment goals. The best solution has been to apply fiducials to the active (I/O) side of the die when patterning the layer. This ensures that the tolerances for both images are matched.
Therein lies the issue, how to reference a downward facing flip chip feature in relation to an upward facing feature on the substrate for post-placement accuracy measurements. See Figure 1. Through the application of Phoseon Technology’s proprietary imaging method and understanding of the application of near infrared inspection algorithms, a process was developed to enable highly accurate and repeatable measurement of the placement of a Flip Chip.
The paper will specifically address the process requirements, challenges of the development of the overall system and the end process data collected. This is intended to show how looking beyond the individual boundaries of “Level 0, 1 or 2” assembly can yield large rewards in solving difficult process issues.
Keywords: Flip Chip, measurement, Infrared
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