MULTI-ROW LEADLESS TAPP - HIGH PERFORMANCE PACKAGING AT VERY FINE PITCHAuthors: Leo M. Higgins III, Ph.D.
Company: ASAT, Inc.
Date Published: 9/25/2005 Conference: SMTA International
Small system size and increasing performance requirements continue to present challenges for low to medium pin count IC packages. These size and performance demands are driving increased usage of leadless packages. The use of fine pitch ball grid array (fpBGA) packages has grown considerably with successive generation of portable and consumer products. The demand for a combination of low thermal resistance, low electrical parasitics, and low profile packaging has lead to massive growth in the use of quad-flat no-lead (QFN) packages. Leadframe-based QFN packages have emerged with two rows of perimeter IOs, increasing the ability for QFNs to provide solutions to higher IO demands. The thin array plastic package (TAPP)* extends the range of the two row QFNs to higher IOs, finer pitches, and higher performance.
TAPP does not use leadframes, with all metal features formed by full additive plating processes on a sacrificial carrier sheet. Since the standard TAPP process does not require use of tie bars to support the inner rows of leads or the die attach pad, TAPP packages can provide up to three rows of perimeter IOs, and/or power and ground rings, a single die attach pad (DAP), or optional multiple electrically isolated DAPs. TAPP packages can also meet emerging very low profile requirements of < 0.5 mm., and very small terminal pads arranged on 0.4 mm pitch, or even finer if market demand develops. As an added benefit, after removal of the carrier, TAPP units are electrically isolated, and immediately suited to Strip-Testing without any added punching or partial saw-cutting. (* TAPP is currently offered by both ASAT and Amkor.)
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