Pan Pacific Symposium Conference Proceedings


A STUDY ON MULTI-CHIP PACKAGE TECHNOLOGY – DUAL CHIP IN TSOP II 54L PACKAGE

Author: Richard Lu
Company: ChipMOS TECHNOLOGIES
Date Published: 1/25/2000   Conference: Pan Pacific Symposium


Seika Machinery, Inc.

Abstract: For the purpose of increasing the integrated density of electronic system, the multi-chip packaging (MCP) technology has become important and popular [1]. Toward the specific application, there are a variety of commercialized proprietary MCP models in the market. This paper describes the MCP technology for extending the capacity of the memory application from 64Mb Synchronized Dynamic Random Access Memory (SDRAM) to 128Mb SDRAM assembled in the TSOP-II 54L package. The package design concept and mold- flow modeling are summarized with the manufacturing process flow of the package. Two chips are bonded in this package in parallel rather than stacked together with a BT substrate as the interposer for electrically interconnecting the signals among the chips and the outer I/O pins. In addition to the new processes for substrate handling, the modification of process parameters is negligible against to current TSOP II 54L processing flow.

Reliability properties are evaluated for the package. It reveals that Moisture Sensitivity Level (MSL) performance could exceed the JEDEC level 3 requirement. The package integrity is proven after 300 cycles Temperature Cycles Tests (TCT). Others environmental evaluations give positive results.



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