Pan Pacific Symposium Conference Proceedings


ASSEMBLY CONCERNS FOR TEST IN STRIP

Author: Bob Fenton
Company: Electroglas, Inc.
Date Published: 2/25/2005   Conference: Pan Pacific Symposium


Abstract: Over the last few years, many of the world's leading semiconductor manufacturers and assembly and test subcontractors have begun testing packaged devices in lead frame, strip or panel format prior to device or package singulation. Test technology advances such as BIST, DFT and higher parallel testers for all applications will accelerate this trend to matrix or strip testing.

As more manufacturers adopt strip testing, greater throughput and flexibility will be required to deal with the dual challenges of increasing cost pressure for metal lead frame devices and the difficulties of contacting the geometries of the latest generation of chip scale packaging. Additionally, new assembly parameters must be considered as they relate to suitability to implement strip testing.

This paper examines the implications of assembly methodology on strip testing. First a short overview of why strip testing is becoming more prevalent followed by case studies of actual strip test implementations. Assembly characteristics such as strip or substrate construction, density and geometry are discussed, emphasizing their effects on overall final test efficiency for several different device types, packages and assembly parameters.

Key words: Final Test, Leadframe, Strip, Matrix, Handler, Wafer Prober.



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