SEMICONDUCTOR PACKAGING TECHNOLOGY DEVELOPMENT TRENDS IN CHINAAuthors: Wei Koh, Ph.D. and Sarah Shen et al.
Company: Kingston Technology
Date Published: 2/25/2005 Conference: Pan Pacific Symposium
In the first part, an overview of the industry product and manufacturing capability from various types of participants are discussed. The technology and product volume leaders are from either foreign multinational OEMs or foreign-local joint-venture enterprises. The second contributors are independent IC packaging service and design houses. The third tier contributors, more likely followers in terms of technical capability, and often neglected by foreign concerns, are the local firms that include state-owned enterprises (SOE), government-sponsored research institutes, universities, domestic packaging companies, and local materials and equipment suppliers.
From the technology point of view, the trend is changing from the dominance of trailing-edge technology packages such as leadframe and ceramic SOP and DIP packages to the more advanced and compact chip scale packages, fine pitch ball grid array, and even wafer level packaging, 3-dimensional stacking, and system in package. Some the fastest growing applications are packages for flash, DRAM, SRAM memories, microcontrollers, and ASICs. Finally, the technical and professional society activities on packaging technology in recent years are also reviewed.
Key words: Semiconductor packaging, China.
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