Pan Pacific Symposium Conference Proceedings


Authors: Kimmo Kaija and Eero Ristolainen
Company: Tampere University of Tech.
Date Published: 2/25/2005   Conference: Pan Pacific Symposium

Abstract: The driving force for the increased integration of electrical devices is to produce more personalized products. The 3D stacked System-in-Package for system integration was modeled and the obtained results were further used in a compact thermal model (CTM) synthesis. Three different thermal RC -networks were used and steady-state and thermal responses of the networks were estimated under several external cooling conditions. The network topology has a large effect on the accuracy of the CTM. A small modification with the network can improve the accuracy significantly.

One reason, why SiP has not yet conquered the electronics industry, is the increased complexity of the design. Especially, the thermal design will require much more attention compared to traditionally packed components [5]. A SiP might contain multiple heat sources in a small volume, surrounded by materials with the low thermal conductivity. This structure can increase the heat dissipation density, shorten the life span of the device, and might endanger the functionality of the system or cause permanent damage. To conclude, the thermal challenges increase the need to verify the design with simulations or prototypes before manufacturing.

Keywords: 3D stacked packaging, thermal modeling, compact thermal model (CTM) synthesis, and System-in-Package (SiP).

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