3D CHIP STACK WITH WAFER THROUGH HOLE TECHNOLOGYAuthor: Chien-Wei Chien et al.
Company: Industrial Tech Research Inst.
Date Published: 2/25/2005 Conference: Pan Pacific Symposium
With the OSP method, high density package of 4 chips were stacked successfully. For a modified test vehicle of higher reliability, the sidewall of the wafer through hole was well treated for the Cu plating and hole filling. Core technologies such as wafer through hole (75µm diameter) processing, high aspect ratio wafer through hole (150µm depth and 75µm diameter) sidewall seed layer and Cu plating and filling were investigated in this study.
Ultraviolet (UV) laser machine was adopted for 75µm diameter wafer through hole drilling in this study. It was found a more inexpensive, higher throughput (compared to ICP) and a large range of processing (hole size down to 20µm and wafer thickness up to 500µm) can be developed. All these reveal a high quality and high compatibility of UV laser machine for wafer through hole drilling.
Among the core technologies, high quality Cu plating for high aspect ratio wafer through hole was required. Seed layer by wafer double-side sputtered Ti/Cu, followed by sidewall treatment with shadow® process for conductive layer were done for higher Cu plating and hole filling quality. It can be found from the results that the through hole can be filled with high quality Cu plating with least void existed.
Keywords: high-density packaging, 3 dimensional stacking, wafer through hole, UV laser.
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