ALIGNED WAFER BONDING FOR 3D INTERCONNECT TECHNOLOGIESAuthor: Matthias Thorsten et al.
Company: EV Group
Date Published: 2/25/2005 Conference: Pan Pacific Symposium
The necessary alignment accuracy is determined by the application and is influenced by he bonding process. Vertical integration of IC devices requires post-bond alignment accuracy of 1µm (3s) or below, whereas 3D integration of IC with MEMS often allows 5µm (3s) or more. Due to metallization layers, high dopant concentrations and single side wafer processing, face-to-face alignment is the most promising method for IC wafer bonding alignment. For MEMS applications backside-, optical- or IR- alignments are viable solutions. The different alignment methods are reviewed and the alignment accuracy is analyzed by means of optical- and IR-microscopy.
Driven by the automotive industry extensive research and development in the field of wafer bonding resulted in a variety of different processes and technologies, which are all field-proven under high volume manufacturing (HVM) conditions. Metal diffusion bonding and low-k adhesive bonding are the most promising approaches for 3D interconnects. In order to enable back thinning of one wafer down to 10µm the bond interface has to be void free, which requires a very high temperature and pressure uniformity.
The bond quality and the occurrence of voids are investigated by means of IR microscopy and Scanning Acoustic Microscopy (SAM).
Aligned wafer bonding is an enabling technology for 3D interconnects and provides viable solutions based on field-proven processes. The technology transfer from R&D equipment and the integration in high-volume production environments will be analyzed.
Key words: 3D interconnect, wafer bonding, wafer alignment.
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