IWLPC (Wafer-Level Packaging) Conference Proceedings


NOVEL LEAD-FREE WAFER-LEVEL UNDERFILL MATERIALS FOR CHIPSCALE PACKAGING

Author: Gyan Dutt et al.
Company: National Starch & Chemical Co.
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Wafer-Level Underfilling is a new process and is still being developed and optimized. It consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process enable the chip manufacturers to move the underfilling step to the wafer-level, thereby eliminating multiple steps in the packaging process. This option of applying underfill is most likely to provide the best economics of any micro-package. However, the new process faces certain technical challenges, particularly with the use of lead-free solders. Further advancement of this technology is necessary to ensure compatibility with lead-free solders, better voiding performance and higher interconnection yield.

We have developed novel wafer level underfill materials for chip scale packaging that are compatible with lead-free assembly. These materials, when coated on the wafer, form clear, transparent coating after B-stage that can be diced into coated dies without any delaminating and cracking. In this paper we discuss the effect of baking in the B-stage step on wafer warpage, underfill cracking, solder paste smearing and underfill flow during the reflow. The material attributes required for controlling solder paste smearing and ensuring solder interconnection are contradictory to each other. The underfill material design and the B-stage step must be controlled tightly to achieve the right working window. The underfill properties, critical for the success of the waferlevel underfill process, are also discussed.

Key Words: wafer-level, underfill, surface mount technology, flip chip, chip scale packaging, lead-free, Bstage.



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