IWLPC (Wafer-Level Packaging) Conference Proceedings


WAFER LEVEL BURN-IN & TEST USING SACRIFICIAL METAL AS AN INTERFACE MEDIUM

Author: John Darling
Company: Delta V Instruments Inc.
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The ability to perform effective burn-in and test at the package level is becoming increasingly difficult as the device complexity and power requirements increase. In addition, the move towards system-on-chip (SOC), stacked memory arrays and multi-chip modules (MCM) is generating a market for known good die (KGD). As the price of Automated Test Equipment (ATE) increases it may be more cost effective to transfer a portion of the functional test over to burn-in.

While a move to wafer level burn-in and test is inevitable, it raises the question, ‘How do we achieve a comprehensive test scenario while ensuring good contact across the wafer surface?’ The use of sacrificial metal (SM) as an interface medium addresses this question by limiting the number of interconnects, so eliminating concerns associated with coefficient of expansion mismatches, planarity issues, and the force required to contact over thirty thousand interface points across the wafer surface.

Key words: burn-in, known good die, KGD, sacrificial metal.



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