IWLPC (Wafer-Level Packaging) Conference Proceedings


WAFER LEVEL PACKAGE TEST STRATEGIES

Authors: Paul Sakamoto and Alfred L. Crouch
Company: Inovys Corporation
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The rapid spread of wafer level packaging (WLP), and other hybrid semiconductor packaging, has brought new demands upon the semiconductor component test flow. In the past, device test quality was assured in multiple test phases that occurred both post fabrication (wafer sort) and post assembly (final or package test). This legacy test process was very adequate to the devices of the time, which were generally individual silicon chips wire bonded to metal lead frames. The wafer sort test was run at reduced specifications, often with a reduced pattern set or set of tests. The post assembly tests were then run at full performance, or as close as the available test equipment would allow, to simulate functional operation of the device. Depending on the device type and technology, there were often more than one test socketing at each of the aforementioned stages.

WLP makes the traditional test flow outlined above both technically and economically unrewarding. New test flows and methodologies must be considered in order to optimize the overall yield and profits from WLP. Principal among the new requirements is that known good die (KGD) test flows are now a necessity to insure high yields in any multi-die packaging scheme. Failure to insure that the individual die are of high quality will result in the loss of the more expensive multi-die packaging as well as any collateral good die that reside in the same package. Assuring this high level of KGD test coverage and quality with minimal test steps and a high level of economy is a difficult challenge, and the focus of this article.

Key words: ATE, test, WLP, KGD, ATPG, DFT, BIST, structural test, functional test, scan, EDA.



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