IWLPC (Wafer-Level Packaging) Conference Proceedings


ELECTROLESS BUMPING FOR LOW K COPPER DEVICE TECHNOLOGY

Authors: T. Teutsch, E. Zakel , T. Oppert
Company: Pac Tech - Packaging Tech.
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: To reduce power consumption and signal delays caused by excess resistance and capacitance, semiconductor industry has introduced new copper based manufacturing processes using 130nm and 100nm device technology. Moving away from traditional Al/SiO2 based process technologies and along with the increase in integration low k dielectrics must be used and are now forcing bumping and interconnection processes to adjust their compatibility.

Flip-Chip Technology once introduced to address signal speed and system performance along with improving the integration density is meanwhile an established driving force for a variety of applications. Flip-Chip, but also wire bonding processes must now develop to meet the challenges of these new semiconductor process technologies.

Bumping processes must be qualified to provide suitable interconnection methods for Copper based semiconductors. Due to it’s high potential for cost reduction, electroless Nickel is a most promising emerging bumping technology, as well as a powerful alternative to the established bumping processes such as C4, sputtering and electroplating.

This Paper gives an overview on the history and development of electroless NiAu as low cost bumping technology in industry. The applications in the first phase of production implementation of electroless Ni/Au were focused on wafers with Al-Pads and Ni/Au as UBM or bump material. The second phase of implementation is focusing on low k wafers with copper pad metallization, and the needs of a low cost final pad finish for thermosonic wire bonding. This opens new dimensions for this technology: as alternative to the sputtered Al- layer, electroless Ni/Au can be used.

An equipment, but also process application roadmap is presented, including 3D stacking of memory devices, via filling, wafer level redistribution, etc..

Keywords: Flip-Chip, Wafer Bumping, Untder Bump Metallization, 300mm, Low K, Copper devices.



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