Author: Gordon Jensen Company: CAD DESIGN SOFTWARE Date Published: 10/10/2004
IWLPC (Wafer-Level Packaging)
Abstract: As Stacked Die, System-in-Package (SiP), and chip-scale packaging become the de-facto standard in the evershrinking world of electronic systems design, complex bond wire and other 3-D clearance issues are becoming increasingly critical in the design and manufacturing process. Traditional 2-D package design tools cannot take into consideration wire bond clearances and die placement tolerances inherent in the manufacturing process, which result in increased trial and error and poor yields as package complexity increases. By utilizing intelligent 3-D tools that perform 3-D Design Rule Checks (DRC) and placement tolerance simulations, bond wire stacked die designs can be optimized for greatly improved yields and reduced manufacturing set up times.
Key words: SiP, System in Package, 3D, Stacked Die.