LEAD vs LEAD-FREE: PACKAGING AND WAFER LEVEL CSP INFLUENCESAuthor: Terence Q. Collier
Date Published: 10/10/2004 Conference: IWLPC (Wafer-Level Packaging)
Unlike some industries where product models don’t change for years, the short product life for semiconductor products demand solutions that can predict reliability, functionality and yield accurately in a timely manner and at economical costs. The goal of this paper is to present a few tried and true, and one or two new processes, for addressing how to improve flip chip test and assembly yield while reducing manufacturing costs. Regardless if the alloy is Pb-free or Pb-rich, solutions to facilitate improved productivity and reliability justify the expenditure. Solutions that further reduce the expenditure while further improving time to market should provide an opportunity to get it right the first time.
Key words: Pb-free, packaging, flip chip, WLP.
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