IWLPC (Wafer-Level Packaging) Conference Proceedings


LEAD vs LEAD-FREE: PACKAGING AND WAFER LEVEL CSP INFLUENCES

Author: Terence Q. Collier
Company: CVInc
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The changeover from Pb-rich (PbR) to Pb-free (PbF) solders can introduce unexpected assembly and test issues that should be modeled early in the process development process. Long term reliability and device performance is important but if the material set chosen is not manufacturable or testable, the proposed solution is not a viable process that should be introduced into production. In addition, the added force required to probe PbF solutions can lead to damage on expensive test hardware. With product life cycles lasting as short as one half year, selecting the incorrect materials or providing inadequate operational settings and having to requalify can lead to missed market opportunity, lost profits and customer dissatisfaction.

Unlike some industries where product models don’t change for years, the short product life for semiconductor products demand solutions that can predict reliability, functionality and yield accurately in a timely manner and at economical costs. The goal of this paper is to present a few tried and true, and one or two new processes, for addressing how to improve flip chip test and assembly yield while reducing manufacturing costs. Regardless if the alloy is Pb-free or Pb-rich, solutions to facilitate improved productivity and reliability justify the expenditure. Solutions that further reduce the expenditure while further improving time to market should provide an opportunity to get it right the first time.

Key words: Pb-free, packaging, flip chip, WLP.



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