IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: Akito Yoshida et al.
Company: Amkor Technology Inc.
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)

Abstract: This paper presents the key assembly technologies and challenges required to insure 3D package robustness and cost effective manufacturing. A variety of threedimensional (3D) packaging technologies have been developed and are gaining wide acceptance for limitedspace applications such as cellular phones, digital cameras, and digital camcorders. Stacking silicon die inside a package allows multiple device types to be integrated into the same space. Single-die and stacked-die Chip Scale Packages (CSP) are being adopted for use in high-density memory or multi-memory products. As an alternative to die stacking, CSP package stacking has been developed as a different approach to 3D packaging, especially for logic plus memory or super high-density memory products. Through the use of package stacking, end customers can benefit from flexibility in the stacked packages in combination with higher product yields.

The enabling technologies to support 3D packaging with limited mounting height are wafer thinning below 100 µm, ultra low loop wire bonding at less than 75 µm, and very thin individual top-gated mold caps that enable packageon-package stacking by placing the terminal pads around the encapsulation area. With these emergent technologies, two types of low profile package-stackable CSPs have been developed for package-on-package configuration. One CSP has 0.3 mm maximum mold cap thickness where a 0.65 mm pitch CSP can be stacked. The other one is a cavity-type CSP with 0.20 mm maximum thick mold. Due to its thin mold cap, 0.50 mm pitch CSP can be stacked on it. Both packages passed MRT JEDEC Level 3 or higher, 1000 cycles of T/C (-55°C/125°C), 1000 hours of HTS (150°C), and 96 hours of HAST (130°C/85%RH).

Key words: CSP, 3D packaging, stacked die, stacked package.

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