WAFER LEVEL PACKAGE CHALLENGES - FABRICATION METHODOLOGY, PACKAGING INFRASTRUCTURE AND DIE-SHRINK CONSIDERATIONSAuthor: Vern Solberg
Company: Tessera, Inc.
Date Published: 10/10/2004 Conference: IWLPC (Wafer-Level Packaging)
Wafer Level Packaging also poses a challenge in designing a die-sized package with a footprint that remains constant despite die-shrink and other changes that are likely to occur from one generation of a die to the next. During the planning phase of the product developers must maintain two significant features: the contact size and pitch selected for the wafer level packaged IC must remain consistent from one die generation to the other, and the array pattern must accommodate efficient conductor routing on the circuit board.
In this paper, the author details a number of wafer level package methodologies, key aspects of the existing assembly infrastructure that should be leveraged or extended, and the planning criteria for the contact array pattern as it relates to die shrink projections. KEY WORDS: Wafer Level Package, WLP, Chip Scale Packaging, CSP, die-size BGA packaging, DSBGA.
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