IWLPC (Wafer-Level Packaging) Conference Proceedings


Author: A.A. Chambers
Company: Surface Technology Systems plc
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Packaging of MEMS devices and the fabrication of 3Dintegrated circuit stacks are currently the focus of wideranging and intensive development activities. In a number of advanced device packaging schemes silicon micromachining processes play a pivotal role. The range of silicon etching applications involved covers the spectrum from uniform wafer thinning, through controlled etching of scribe channels and vias with precisely-controlled sidewall slope and base width, to micro-machining of high aspectratio through-wafer vias.

This paper describes specific silicon micro-machining processes that have been developed in inductively coupled plasma (ICP) etching systems for a number of these applications. In particular, dry-etching techniques for fabricating through-wafer vias with vertical sidewall profiles, high etching rate and high selectivity to photoresist masks are discussed and contrasted with micro-machining techniques for forming scribe channels and vias with specific dimensional control and predictable sidewall taper angles.

Keywords: DRIE, deep reactive ion etching, micromachining, anisotropic etching, tapered etching, Bosch process

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