Pan Pacific Symposium Conference Proceedings


Author: Scott Joslin
Company: Motorola
Date Published: 1/25/2000   Conference: Pan Pacific Symposium

Abstract: Motorola’s implementation of a high volume low cost flip chip assembly process required IC bumping operations, printed circuit board design, and manufacturing issues to be addressed. The electroplated bumps were eutectic tin/lead with a copper stud under bump metallurgy (UBM) customized to 45 microns. The copper stud maintains the post-reflow silicon to printed circuit board standoff.

Careful attention to detail was maintained during the printed circuit board design. FR-4 with an electroless nickel/gold surface finish was the substrate of choice due to its low cost relative to BT and HDI. The PCB layout had to adhere to design rules acceptable to high volume low technology PCB houses. Consequently, the limitations of the circuit board fabricators determined the silicon redistribution, bump pitch, bump size, and the placement equipment requirements.

Incorporating flip chip assembly into an existing SMT production line posed significant challenges to the factory. Fluxing, die placement, underfill and cure operations required characterization prior to production ramp up. Manufacturing process windows were defined and implemented to avoid potentially expensive flip chip yield losses due to skewed die, opens, shorts etc.

The use of innovative fabrication and design techniques has allowed Motorola to successfully ship several million pagers incorporating a low cost flip chip assembly. In addition to providing a substantial contribution to Motorola’s bottom line, the flip chip process has demonstrated excellent assembly yields and field reliability.

Key words: Flip Chip, DCA, solder bumps, SMT

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