IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: E. Jan Vardaman and Linda Matthew
Company: TechSearch International, Inc.
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)

Abstract: A noteworthy development in IC assembly and packaging is the growth of die packaged at the wafer level - either in flip chip or wafer level packages (WLPs). Flip chip has been around as an interconnect method since the 1960s. Most of the flip chip growth is in the area of flip-chip-in-package (FCIP). Growth in WLPs is driven by the expansion in portable and consumer products. This presentation will focus on the trends in flip chip and wafer level packaging and will examine the growing number of applications for each of these technologies.

The drivers for flip chip continue to be performance and pad limited designs, as well as form factor needs. For these applications, almost all are 0.13µm device technologies. High performance logic suppliers such as ASIC, field programmable gate array (FPGA), and microprocessor makers are expanding their use of FCIP. In addition, highend DSPs, graphics ICs, and chip set makers are also increasing shipments of FCIP. Growth rates for solder bumping are expected to increase 48 percent in 2005. This growth is driven by chipset, graphics, and wireless applications.

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